1. Field of the Invention
This invention generally relates to systems and methods for evaluating and controlling semiconductor fabrication processes. Certain embodiments relate to systems and methods for evaluating and/or controlling a lithography process by measuring a property of a resist and controlling a process step involved in the lithography process.
2. Description of the Related Art
Semiconductor fabrication processes typically involve a number of lithography steps to form various features and multiple levels of a semiconductor device. Lithography involves transferring a pattern to a resist formed on a semiconductor substrate, which may be commonly referred to as a wafer. A reticle, or a mask, may be disposed above the resist and may have substantially transparent regions and substantially opaque regions configured in a pattern that may transferred to the resist. As such, substantially opaque regions of the reticle may protect underlying regions of the resist from exposure to an energy source. The resist may, therefore, be patterned by selectively exposing regions of the resist to an energy source such as ultraviolet light, a beam of electrons, or an x-ray source. The patterned resist may then be used to mask underlying layers in subsequent semiconductor fabrication processes such as ion implantation and etch. Therefore, a resist may substantially inhibit an underlying layer such as a dielectric material or the semiconductor substrate from implantation of ions or removal by etch.
As the features sizes of semiconductor devices continue to shrink, the minimum feature size which may be successfully fabricated may often be limited by performance characteristics of a lithography process. Examples of performance characteristics of a lithography process include, but are not limited to, resolution capability, across chip linewidth variations, and across wafer linewidth variations. In optical lithography, performance characteristics such as resolution capability of the lithography process may often be limited by the quality of the resist application, the performance of the resist, the exposure tool, and the wavelength of light which is used to expose the resist. The ability to resolve a minimum feature size, however, may also be strongly dependent on other critical parameters of the lithography process such as a temperature of a post exposure bake process or an exposure dose of an exposure process. As such, controlling the critical parameters of lithography processes is becoming increasingly important to the successful fabrication of semiconductor devices.
One strategy to improve the performance characteristics of a lithography process may involve controlling and reducing variations in critical parameters of the lithography process. For example, one critical parameter in a lithography process may be the post exposure bake temperature. In particular, a chemical reaction in an exposed portion of a chemically amplified resist may be driven and controlled by heating the resist subsequent to the exposure process. Such a resist may include, but may not be limited to, a resin and a photo-acid generating compound. The temperature of a post exposure bake process may drive generation and diffusion of a photo-generated acid in the resist that causes deblocking of the resin. Deblocking of the resin may substantially alter the solubility of the resist such that it may be removed by exposure to an aqueous developer solution in a subsequent developing process. As such, temperature-controlled diffusion in the exposed resist may affect physical dimensions of remaining resist, or resolved features. Furthermore, variations in temperature across a bake plate of a post exposure bake process module may cause variations in the dimensions of the features at various positions on a wafer. Therefore, the resolution capability of a lithography process may be improved by reducing temperature variations across the bake plate of a post exposure bake process module.
There are several disadvantages, however, in using currently available methods to improve the resolution capability of lithography processes. For example, currently available methods may not account for degradation in the uniformity of a critical parameter over time. For a post exposure bake module, thermal relaxation of heating elements, contamination, or other performance variations may adversely affect the resolution capability of a lithography process to various degrees over time. As such, monitoring and controlling time-dependent variations in the critical parameters may maintain and improve the performance characteristics of a lithography process. In addition, integrated control mechanisms that may currently be used to monitor variations in the temperature of the post exposure bake module may control and alter the process at the wafer level. Therefore, all positions, or fields, on the wafer are affected equally and improvements are made for an average performance across the wafer. In this manner, systematic variations in the resolution capability from field to field across a wafer may not be monitored or altered, which may have an adverse affect on the overall performance characteristics of a lithography process.
Accordingly, it may be advantageous to develop a method and a system to evaluate and control a lithography process such that within wafer variability of critical dimensions of features formed by a lithography process may be reduced.
An embodiment of the invention relates to a method for reducing within wafer (xe2x80x9cWIWxe2x80x9d) variation of a critical metric of a lithography process. A critical metric of a lithography process may include, but is not limited to, a critical dimension of features formed during the lithography process and overlay. Critical dimensions of features formed during a lithography process may include, for example, a width, a height, and a sidewall profile of the features. Overlay generally refers to a lateral position of a feature on one level of a wafer with respect to a lateral position of a feature on another level of the wafer. The lithography process may include optical lithography, e-beam lithography, or x-ray lithography.
The method may include measuring at least one property of a resist disposed upon a wafer during the lithography process. For example, the method may include measuring at least the one property of the resist at various locations across the wafer. In addition, the method may include measuring at least the one property of the resist between steps of the lithography process or during a step of the lithography process. Furthermore, the method may include measuring at least one property of a resist disposed upon at least two wafers during the lithography process. At least the one property may include, but may not be limited to, a thickness, an index of refraction, an extinction coefficient, a linewidth of a latent image, a height of a latent image, a width of a feature, a height of a feature, overlay, or any combination thereof. A latent image generally refers to an image that may be formed in an exposed resist subsequent to a post exposure bake process.
The method may further include altering at least one parameter of a process module, configured to perform a step of the lithography process, in response to at least the one measured property of the resist. In this manner, within wafer variation of a critical metric may be reduced. The process module may include, but may not be limited to, a surface preparation module, a coat module, a bake module, an expose module, or a develop module. In addition, if at least one property of a resist disposed upon at least two wafers is measured, then the method may include altering at least one parameter of a process module in response to at least the one measured property of the resist disposed upon at least the two wafers. At least the one parameter may be altered using a feedback control technique, a feedforward control technique, an in situ control technique, or any combination thereof.
Altering at least the one parameter may include processing a first portion of a wafer with a first set of process conditions during the step and processing a second portion of the wafer with a second set of process conditions during the step. For example, if at least the one measured property includes thickness variation across the wafer, then a portion of the wafer coated with a thicker resist may be exposed with a higher exposure dose than a portion of the wafer coated with a thinner resist in response to the measured thickness variation. In an additional example, a portion of a wafer coated with a thicker resist may be heated to a higher temperature during a post exposure bake process than a portion of the wafer coated with a thinner resist in response to a measured thickness variation. In this manner, process conditions of a lithography process step may vary across a wafer such that a critical metric of the lithography process may be substantially uniform across the wafer despite variations in resist properties.
An additional embodiment relates to a system configured to reduce within wafer variation of a critical metric of a lithography process. The critical metric may include a critical dimension of a feature formed by the lithography process or any of the critical metrics as described above. The system may include at least one measurement device. At least the one measurement device may be configured to measure at least one property of a resist disposed upon a wafer during the lithography process. For example, at least the one measurement device may be configured to measure at least the one property of the resist at various locations across the wafer. In addition, at least the one measurement device may be configured to measure at least the one property of the resist between steps of the lithography process. Alternatively, at least the one measurement device may be configured to measure at least the one property of the resist during a step of the lithography process. For example, a measurement device may be integrated into a lithography cluster tool as described herein. Because a property of the resist may be measured during a lithography process, a method as described herein may have a quicker turn around time than conventional lithography process control methods. Therefore, a method as described herein may yield a larger number of semiconductor devices having relatively high performance bin characteristics. At least the one property may include any of the properties as described herein.
The system may also include a process module configured to perform a step of the lithography process. The process module may include, for example, a surface preparation module, a coat module, a bake module, an expose module, or a develop module. At least one parameter of the process module may be altered in response to at least the one measured property such that the within wafer variation of the critical metric may be reduced. In addition, at least the one parameter of the process module may be altered using a feedback control technique, a feedforward control technique, an in situ control technique, or any combination thereof. At least the one parameter of the process module may also be altered such that a first portion of the wafer can be processed with a first set of process conditions during the step and such that a second portion of the wafer can be processed with a second set of process conditions during the step.
The system may also include a controller computer coupled to at least the one measurement device and the process module. The controller computer may be configured to receive at least one measured property of the resist from the measurement device. The controller computer may also be configured to alter at least one parameter of the process module in response to at least the one measured property.
A further embodiment relates to a method for fabricating a semiconductor device. For example, the method may include measuring at least one property of a resist disposed upon a wafer during a lithography process. The method may also include altering at least one parameter of at least one process module in response to at least the one measured property of the resist to reduce within wafer variation of a critical metric of the lithography process. In addition, the method may include processing the wafer to form at least a portion of at least one semiconductor device upon the wafer. For example, processing the wafer may include etching, ion implantation, deposition, chemical mechanical polishing, or plating. In this manner, semiconductor devices formed by the method may have higher performance bin distributions thereby improving not only yield but also high margin product yield.